1. Field of the Invention
Embodiments of the invention relate to switching power supplies in which rising up performance of an output voltage is improved at a startup period of the power supplies.
2. Description of the Related Art
FIG. 5 shows a schematic construction of a conventionally common switching power supply of a forward type. The switching power supply receives an input voltage Vin that is obtained by full-wave rectification of an AC voltage Vac with a diode bridge circuit DS1 and following smoothing with an input capacitor Cin. The switching power supply is mainly composed of a switching power supply main body 1 provided with a switching element Q that switches the input voltage Vin through a primary winding Ta of a transformer T. The switching power supply main body 1 rectifies an AC voltage generated across a secondary winding Tb of the transformer T with diodes DS2 and DS3, and make the rectified voltage smooth with a smoothing circuit composed of a reactor L and an output capacitor C-out to obtain a specified output voltage Vout.
A power supply IC 2 is a control circuit for ON/OFF-driving the switching element Q. The power supply IC 2 controls driving of the switching element Q basically according to an FB signal given by an output voltage detecting circuit 3 for detecting the output voltage Vout. More specifically, the power supply IC 2, a control circuit, conducts feedback control of a pulse width, i.e. an ON width, of the driving signal for ON/OFF-switching of the switching element Q according to the FB signal. The output voltage detecting circuit 3 detects the output voltage Vout divided with series-connected resistors Ra and Rb. The output voltage detecting circuit 3 delivers the FB signal to the power supply IC 2 through a photo-coupler PC, the FB signal being an error voltage between a voltage set at the shunt regulator SR and a voltage detected with the resistances Ra and Rb.
A power supply input terminal VCC of the power supply IC 2 is supplied with a startup current from the diode bridge circuit DS1 through a resistor R. The startup current charges a capacitor C connected to the power supply input terminal VCC. The power supply IC 2 starts driving the switching element Q when the charged voltage on the capacitor C exceeds a releasing voltage of an under voltage lock out circuit (an UVLO circuit) in the power supply IC 2. When the switching power supply main body 1 begins operation upon starting up of driving the switching element Q, a voltage developed across an auxiliary winding Tc of the transformer T is given to the power supply input terminal VCC through a diode D. After that, the power supply IC 2 operates receiving the voltage delivered from the auxiliary winding Tc through the diode D.
The power supply IC 2 is basically constructed as shown in FIG. 6. The power supply IC 2 comprises an oscillator 21 of a voltage controlled type. The fundamental oscillation frequency of the oscillator 21 is regulated according to the resistance of an external resistance (not shown in the figure) connected to the terminal RT. The oscillator 21 generates a signal with a triangular waveform using charging and discharging process of a capacitor (not shown in the figure) contained in the oscillator 21 as well as a signal with a rectangular waveform in synchronous with the signal with the triangular waveform. A comparator 22 for PWM control compares the signal with the triangular waveform generated in the oscillator 21 with the FB signal and compares the signal with the triangular waveform with a CS signal for soft starting that is generated at the startup of the power supply IC 2 and gradually increases from zero volts. According to the comparison result, the comparator 22 generates a control signal with a pulse width that regulates the ON width of the switching element Q.
More specifically as shown in FIG. 7, the comparator 22 generates the control signal of the pulse width from the timing of a lowest voltage or a bottom of the signal with triangular waveform to the timing at which the voltage with triangular waveform exceeds either one of the FB signal and the CS signal. This control signal is given to an output driver circuit 23 under an operation condition for the switching power supply main body 1, and from the output driver circuit 23, a driving signal OUT for ON/OFF-driving the switching element Q is delivered.
The oscillator 21 is given, through a frequency reducing circuit 24, a VF signal that varies according to the driving signal OUT for switching the switching element Q. The VF voltage is, in the case of forward type switching power supply, a voltage proportional to an ON duty, which is the smoothed driving signal OUT. The frequency reducing circuit 24, when the overload detecting circuit 25 detects an overload protection (OLP) of the switching power supply main body 1, controls the operation of the oscillator 21 corresponding to the VF voltage. More specifically, the frequency reducing circuit 24, when an OLP is detected and the VF voltage is a low voltage that does not reach a predetermined threshold voltage, decreases the oscillation frequency of the oscillator 21 corresponding to the VF voltage, thus the switching frequency of the switching element Q is decreased.
The control to decrease the switching frequency restricts the output current of the switching power supply main body 1 in the event of OLP. According to the output current control, an output voltage-output current characteristic of the switching power supply exhibits a current drooping characteristic as shown in FIG. 8. Japanese Unexamined Patent Application Publication No. 2002-300777 (also referred to herein as “Patent Document 1”) discloses a now widely known protection technology in which the switching frequency is reduced in an event of overload to droop the output current, thereby avoiding delivering overcurrent to the load in the secondary side in a switching power supply.
A comparator 26 in FIG. 6 detects overcurrent through the switching element Q from the signal given to an IS terminal, and a comparator 27 detects overload from the FB signal. The comparator 28 judges a voltage at the power supply input terminal VCC for under-voltage locking out (UVLO). The power supply IC 2 of FIG. 6 further comprises an internal power supply 41 for 5 V and an initialization circuit 42 for generating an initial resetting signal.
In the switching power supply described above, when the voltage given at the power supply input terminal VCC increases after startup of the power supply and exceeds the voltage for under-voltage locking out of the power supply IC 2, the under-voltage locking out function is released, and current supply begins to the FB terminal and the CS terminal, to which respective capacitors are connected, of the power supply IC 2. When an FB signal and a CS signal at the FB terminal and the CS terminal exceed predetermined value, the oscillator 21 starts oscillation operation.
Immediately after startup of the switching power supply, the power supply IC 2 starts driving the switching element Q in a normal mode. With this operation, the voltage of the FB signal becomes high as shown in FIG. 9. When the voltage of the FB signal exceeds a predetermined threshold value Vth for overload protection (OLP), the power supply IC 2 transfers from the normal mode to an overload mode. In this startup period, the VF voltage grows slowly with the driving operation of the switching element Q. As a result, the current drooping control on the output current works simultaneously with the transition to the overload mode. Consequently, the switching frequency of the switching element Q decreases accompanying the transition to the overload mode.
However, in the case the DC output voltage Vout fast rises up in the startup period, or in the case the transition to the overload mode occurs during the rising period of the output voltage Vout, the frequency of the driving signal OUT, which is a switching frequency of the switching element Q, decreases abruptly as shown in FIG. 9. As a consequence, the increase in the DC output voltage Vout temporarily stops with the transition to the overload mode. Thus, the ascending curve of the DC output voltage Vout becomes so-called stepwise as the part indicated by the broken circle in the bottom figure in FIG. 9. If the DC output voltage Vout does not exhibit a monotonic increase characteristic, it may cause power ON resetting of an IC in the subsequent stage connected to the secondary side output terminal, or malfunction of the under-voltage locking out function.